The present invention relates generally to computer memory, and more specifically to memory cell presetting for improved memory performance.
It is a common characteristic of storage class memories to have asymmetric read and write latencies. Typically, write latencies are slower than read latencies. Phase-change memory (PCM) is an example of a non-volatile memory that has asymmetric read-write latency, where the write latency is much higher (about 8×) compared to the read latency.
PCM is a non-volatile memory that exploits the property of chalcogenide glass (GST) to switch the material between two states, amorphous and polycrystalline. The amorphous phase has high resistance and the polycrystalline phase has low resistance. The difference in resistivity between the two states is three to five orders of magnitude and data is stored in the form of resistance. The state of a PCM device is changed by applying heat through the use of electrical pulses. Different heat-time profiles are used to switch from one phase to another.
A PCM memory cell can typically be programmed into two states, typically referred to as RESET and SET states. The RESET state is characterized by a high cell resistance value, whereas the SET state is characterized by low cell resistance value.
To RESET the device, a high power pulse of short duration is required. This electrical pulse first raises the temperature of the PCM material above its melting point, typically in excess of 600° C., and is then quickly terminated. The small region of melted material subsequently cools extremely quickly as a result of thermal conduction into the surroundings. This extremely rapid cooling process locks the PCM material into an amorphous state. The small dimensions of typical PCM devices results in a thermal time constant on the order of a few nanoseconds, and thus RESET pulses are short. RESET latency is typically similar to the read latency associated with a PCM cell.
To SET a cell, the amorphous material must be encouraged to crystallize into a polycrystalline state having a lower electrical resistance. This can be accomplished by heating the material above its crystallization temperature but below its melting point for a sufficient length of time. The SET time is limited by the maximum crystallization rate of the material. Reliably crystallizing typical PCM cells made of GST requires heating pulses that are hundreds of nanoseconds in duration. Therefore, the SET latency is much higher (about 8×) compared to the RESET latency. This implies that PCM is not only read-write asymmetric, but also has non-uniformity in the write times. In other words it has data-dependent write latency.
Given that a memory line contains hundreds of bits, it is highly likely, when writing, that both RESET and SET transitions will occur, hence the write latency of PCM array is determined by the slower of the two operations.
Similar considerations apply to the write energy, which is also asymmetric between RESET and SET states. The same considerations can be easily extended to multi-bit devices.